    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv.inc
    GET cydevicerv_trm.inc

; ADC_DelSig_1_Ext_CP_Clk
ADC_DelSig_1_Ext_CP_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
ADC_DelSig_1_Ext_CP_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
ADC_DelSig_1_Ext_CP_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
ADC_DelSig_1_Ext_CP_Clk__CFG2_SRC_SEL_MASK EQU 0x07
ADC_DelSig_1_Ext_CP_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
ADC_DelSig_1_Ext_CP_Clk__PM_ACT_MSK EQU 0x01
ADC_DelSig_1_Ext_CP_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
ADC_DelSig_1_Ext_CP_Clk__PM_STBY_MSK EQU 0x01

; ADC_DelSig_1_theACLK
ADC_DelSig_1_theACLK__CFG0 EQU CYREG_CLKDIST_ACFG0_CFG0
ADC_DelSig_1_theACLK__CFG1 EQU CYREG_CLKDIST_ACFG0_CFG1
ADC_DelSig_1_theACLK__CFG2 EQU CYREG_CLKDIST_ACFG0_CFG2
ADC_DelSig_1_theACLK__CFG2_SRC_SEL_MASK EQU 0x07
ADC_DelSig_1_theACLK__CFG3 EQU CYREG_CLKDIST_ACFG0_CFG3
ADC_DelSig_1_theACLK__CFG3_PHASE_DLY_MASK EQU 0x0F
ADC_DelSig_1_theACLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG1
ADC_DelSig_1_theACLK__PM_ACT_MSK EQU 0x01
ADC_DelSig_1_theACLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG1
ADC_DelSig_1_theACLK__PM_STBY_MSK EQU 0x01

; ADC_DelSig_1_DSM2
ADC_DelSig_1_DSM2__BUF0 EQU CYREG_DSM0_BUF0
ADC_DelSig_1_DSM2__BUF1 EQU CYREG_DSM0_BUF1
ADC_DelSig_1_DSM2__BUF2 EQU CYREG_DSM0_BUF2
ADC_DelSig_1_DSM2__BUF3 EQU CYREG_DSM0_BUF3
ADC_DelSig_1_DSM2__CLK EQU CYREG_DSM0_CLK
ADC_DelSig_1_DSM2__CR0 EQU CYREG_DSM0_CR0
ADC_DelSig_1_DSM2__CR1 EQU CYREG_DSM0_CR1
ADC_DelSig_1_DSM2__CR10 EQU CYREG_DSM0_CR10
ADC_DelSig_1_DSM2__CR11 EQU CYREG_DSM0_CR11
ADC_DelSig_1_DSM2__CR12 EQU CYREG_DSM0_CR12
ADC_DelSig_1_DSM2__CR13 EQU CYREG_DSM0_CR13
ADC_DelSig_1_DSM2__CR14 EQU CYREG_DSM0_CR14
ADC_DelSig_1_DSM2__CR15 EQU CYREG_DSM0_CR15
ADC_DelSig_1_DSM2__CR16 EQU CYREG_DSM0_CR16
ADC_DelSig_1_DSM2__CR17 EQU CYREG_DSM0_CR17
ADC_DelSig_1_DSM2__CR2 EQU CYREG_DSM0_CR2
ADC_DelSig_1_DSM2__CR3 EQU CYREG_DSM0_CR3
ADC_DelSig_1_DSM2__CR4 EQU CYREG_DSM0_CR4
ADC_DelSig_1_DSM2__CR5 EQU CYREG_DSM0_CR5
ADC_DelSig_1_DSM2__CR6 EQU CYREG_DSM0_CR6
ADC_DelSig_1_DSM2__CR7 EQU CYREG_DSM0_CR7
ADC_DelSig_1_DSM2__CR8 EQU CYREG_DSM0_CR8
ADC_DelSig_1_DSM2__CR9 EQU CYREG_DSM0_CR9
ADC_DelSig_1_DSM2__DEM0 EQU CYREG_DSM0_DEM0
ADC_DelSig_1_DSM2__DEM1 EQU CYREG_DSM0_DEM1
ADC_DelSig_1_DSM2__MISC EQU CYREG_DSM0_MISC
ADC_DelSig_1_DSM2__OUT0 EQU CYREG_DSM0_OUT0
ADC_DelSig_1_DSM2__OUT1 EQU CYREG_DSM0_OUT1
ADC_DelSig_1_DSM2__REF0 EQU CYREG_DSM0_REF0
ADC_DelSig_1_DSM2__REF1 EQU CYREG_DSM0_REF1
ADC_DelSig_1_DSM2__REF2 EQU CYREG_DSM0_REF2
ADC_DelSig_1_DSM2__REF3 EQU CYREG_DSM0_REF3
ADC_DelSig_1_DSM2__RSVD1 EQU CYREG_DSM0_RSVD1
ADC_DelSig_1_DSM2__SW0 EQU CYREG_DSM0_SW0
ADC_DelSig_1_DSM2__SW2 EQU CYREG_DSM0_SW2
ADC_DelSig_1_DSM2__SW3 EQU CYREG_DSM0_SW3
ADC_DelSig_1_DSM2__SW4 EQU CYREG_DSM0_SW4
ADC_DelSig_1_DSM2__SW6 EQU CYREG_DSM0_SW6
ADC_DelSig_1_DSM2__TR0 EQU CYREG_NPUMP_DSM_TR0
ADC_DelSig_1_DSM2__TST0 EQU CYREG_DSM0_TST0
ADC_DelSig_1_DSM2__TST1 EQU CYREG_DSM0_TST1

; ADC_DelSig_1_DEC
ADC_DelSig_1_DEC__COHER EQU CYREG_DEC_COHER
ADC_DelSig_1_DEC__CR EQU CYREG_DEC_CR
ADC_DelSig_1_DEC__DR1 EQU CYREG_DEC_DR1
ADC_DelSig_1_DEC__DR2 EQU CYREG_DEC_DR2
ADC_DelSig_1_DEC__DR2H EQU CYREG_DEC_DR2H
ADC_DelSig_1_DEC__GCOR EQU CYREG_DEC_GCOR
ADC_DelSig_1_DEC__GCORH EQU CYREG_DEC_GCORH
ADC_DelSig_1_DEC__GVAL EQU CYREG_DEC_GVAL
ADC_DelSig_1_DEC__OCOR EQU CYREG_DEC_OCOR
ADC_DelSig_1_DEC__OCORH EQU CYREG_DEC_OCORH
ADC_DelSig_1_DEC__OCORM EQU CYREG_DEC_OCORM
ADC_DelSig_1_DEC__OUTSAMP EQU CYREG_DEC_OUTSAMP
ADC_DelSig_1_DEC__OUTSAMPH EQU CYREG_DEC_OUTSAMPH
ADC_DelSig_1_DEC__OUTSAMPM EQU CYREG_DEC_OUTSAMPM
ADC_DelSig_1_DEC__OUTSAMPS EQU CYREG_DEC_OUTSAMPS
ADC_DelSig_1_DEC__PM_ACT_CFG EQU CYREG_PM_ACT_CFG10
ADC_DelSig_1_DEC__PM_ACT_MSK EQU 0x01
ADC_DelSig_1_DEC__PM_STBY_CFG EQU CYREG_PM_STBY_CFG10
ADC_DelSig_1_DEC__PM_STBY_MSK EQU 0x01
ADC_DelSig_1_DEC__SHIFT1 EQU CYREG_DEC_SHIFT1
ADC_DelSig_1_DEC__SHIFT2 EQU CYREG_DEC_SHIFT2
ADC_DelSig_1_DEC__SR EQU CYREG_DEC_SR
ADC_DelSig_1_DEC__TRIM__16H EQU CYREG_FLSHID_CUST_TABLES_DEC_16H
ADC_DelSig_1_DEC__TRIM__16L EQU CYREG_FLSHID_CUST_TABLES_DEC_16L
ADC_DelSig_1_DEC__TRIM__1H EQU CYREG_FLSHID_CUST_TABLES_DEC_1H
ADC_DelSig_1_DEC__TRIM__1L EQU CYREG_FLSHID_CUST_TABLES_DEC_1L
ADC_DelSig_1_DEC__TRIM__4H EQU CYREG_FLSHID_CUST_TABLES_DEC_4H
ADC_DelSig_1_DEC__TRIM__4L EQU CYREG_FLSHID_CUST_TABLES_DEC_4L
ADC_DelSig_1_DEC__TRIM__P25H EQU CYREG_FLSHID_CUST_TABLES_DEC_P25H
ADC_DelSig_1_DEC__TRIM__P25L EQU CYREG_FLSHID_CUST_TABLES_DEC_P25L

; ADC_DelSig_1_IRQ
ADC_DelSig_1_IRQ__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
ADC_DelSig_1_IRQ__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
ADC_DelSig_1_IRQ__INTC_MASK EQU 0x20000000
ADC_DelSig_1_IRQ__INTC_NUMBER EQU 29
ADC_DelSig_1_IRQ__INTC_PRIOR_NUM EQU 7
ADC_DelSig_1_IRQ__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_29
ADC_DelSig_1_IRQ__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
ADC_DelSig_1_IRQ__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; Opamp_1_ABuf
Opamp_1_ABuf__CR EQU CYREG_ABUF0_CR
Opamp_1_ABuf__MX EQU CYREG_ABUF0_MX
Opamp_1_ABuf__NPUMP_ABUF_TR0 EQU CYREG_NPUMP_ABUF_TR0
Opamp_1_ABuf__PM_ACT_CFG EQU CYREG_PM_ACT_CFG4
Opamp_1_ABuf__PM_ACT_MSK EQU 0x01
Opamp_1_ABuf__PM_STBY_CFG EQU CYREG_PM_STBY_CFG4
Opamp_1_ABuf__PM_STBY_MSK EQU 0x01
Opamp_1_ABuf__RSVD EQU CYREG_ABUF0_RSVD
Opamp_1_ABuf__SW EQU CYREG_ABUF0_SW
Opamp_1_ABuf__TR0 EQU CYREG_ABUF0_TR0
Opamp_1_ABuf__TR1 EQU CYREG_ABUF0_TR1

; Opamp_2_ABuf
Opamp_2_ABuf__CR EQU CYREG_ABUF3_CR
Opamp_2_ABuf__MX EQU CYREG_ABUF3_MX
Opamp_2_ABuf__NPUMP_ABUF_TR0 EQU CYREG_NPUMP_ABUF_TR0
Opamp_2_ABuf__PM_ACT_CFG EQU CYREG_PM_ACT_CFG4
Opamp_2_ABuf__PM_ACT_MSK EQU 0x08
Opamp_2_ABuf__PM_STBY_CFG EQU CYREG_PM_STBY_CFG4
Opamp_2_ABuf__PM_STBY_MSK EQU 0x08
Opamp_2_ABuf__RSVD EQU CYREG_ABUF3_RSVD
Opamp_2_ABuf__SW EQU CYREG_ABUF3_SW
Opamp_2_ABuf__TR0 EQU CYREG_ABUF3_TR0
Opamp_2_ABuf__TR1 EQU CYREG_ABUF3_TR1

; SPIS_1_BSPIS
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB12_MSK
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB12_ST
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SPIS_1_BSPIS_es2_SPISlave_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SPIS_1_BSPIS_es2_SPISlave_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__COUNT_REG EQU CYREG_B0_UDB12_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SPIS_1_BSPIS_es2_SPISlave_BitCounter__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SPIS_1_BSPIS_es2_SPISlave_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__3__MASK EQU 0x08
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__3__POS EQU 3
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__4__MASK EQU 0x10
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__4__POS EQU 4
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__5__MASK EQU 0x20
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__5__POS EQU 5
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__6__MASK EQU 0x40
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__6__POS EQU 6
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__MASK EQU 0x78
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__MASK_REG EQU CYREG_B0_UDB13_MSK
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SPIS_1_BSPIS_es2_SPISlave_RxStsReg__STATUS_REG EQU CYREG_B0_UDB13_ST
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__0__MASK EQU 0x01
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__0__POS EQU 0
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__1__MASK EQU 0x02
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__1__POS EQU 1
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__2__MASK EQU 0x04
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__2__POS EQU 2
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__6__MASK EQU 0x40
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__6__POS EQU 6
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__MASK EQU 0x47
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__MASK_REG EQU CYREG_B0_UDB15_MSK
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SPIS_1_BSPIS_es2_SPISlave_TxStsReg__STATUS_REG EQU CYREG_B0_UDB15_ST
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__A0_REG EQU CYREG_B0_UDB14_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__A1_REG EQU CYREG_B0_UDB14_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__D0_REG EQU CYREG_B0_UDB14_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__D1_REG EQU CYREG_B0_UDB14_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__F0_REG EQU CYREG_B0_UDB14_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u0__F1_REG EQU CYREG_B0_UDB14_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__A0_A1_REG EQU CYREG_B0_UDB15_A0_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__A0_REG EQU CYREG_B0_UDB15_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__A1_REG EQU CYREG_B0_UDB15_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__D0_D1_REG EQU CYREG_B0_UDB15_D0_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__D0_REG EQU CYREG_B0_UDB15_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__D1_REG EQU CYREG_B0_UDB15_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__DP_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__F0_F1_REG EQU CYREG_B0_UDB15_F0_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__F0_REG EQU CYREG_B0_UDB15_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMISO_u1__F1_REG EQU CYREG_B0_UDB15_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__A0_REG EQU CYREG_B0_UDB12_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__A1_REG EQU CYREG_B0_UDB12_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__D0_REG EQU CYREG_B0_UDB12_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__D1_REG EQU CYREG_B0_UDB12_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__F0_REG EQU CYREG_B0_UDB12_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__F1_REG EQU CYREG_B0_UDB12_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__A0_REG EQU CYREG_B0_UDB13_A0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__A1_REG EQU CYREG_B0_UDB13_A1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__D0_REG EQU CYREG_B0_UDB13_D0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__D1_REG EQU CYREG_B0_UDB13_D1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__F0_REG EQU CYREG_B0_UDB13_F0
SPIS_1_BSPIS_es2_SPISlave_sR16_DpMOSI_u1__F1_REG EQU CYREG_B0_UDB13_F1

; RTC_1_isr
RTC_1_isr__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
RTC_1_isr__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
RTC_1_isr__INTC_MASK EQU 0x200000
RTC_1_isr__INTC_NUMBER EQU 21
RTC_1_isr__INTC_PRIOR_NUM EQU 7
RTC_1_isr__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
RTC_1_isr__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
RTC_1_isr__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; CLOCK
CLOCK__0__MASK EQU 0x20
CLOCK__0__PC EQU CYREG_PRT4_PC5
CLOCK__0__PORT EQU 4
CLOCK__0__SHIFT EQU 5
CLOCK__AG EQU CYREG_PRT4_AG
CLOCK__AMUX EQU CYREG_PRT4_AMUX
CLOCK__BIE EQU CYREG_PRT4_BIE
CLOCK__BIT_MASK EQU CYREG_PRT4_BIT_MASK
CLOCK__BYP EQU CYREG_PRT4_BYP
CLOCK__CTL EQU CYREG_PRT4_CTL
CLOCK__DM0 EQU CYREG_PRT4_DM0
CLOCK__DM1 EQU CYREG_PRT4_DM1
CLOCK__DM2 EQU CYREG_PRT4_DM2
CLOCK__DR EQU CYREG_PRT4_DR
CLOCK__INP_DIS EQU CYREG_PRT4_INP_DIS
CLOCK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
CLOCK__LCD_EN EQU CYREG_PRT4_LCD_EN
CLOCK__MASK EQU 0x20
CLOCK__PORT EQU 4
CLOCK__PRT EQU CYREG_PRT4_PRT
CLOCK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
CLOCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
CLOCK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
CLOCK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
CLOCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
CLOCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
CLOCK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
CLOCK__PS EQU CYREG_PRT4_PS
CLOCK__SHIFT EQU 5
CLOCK__SLW EQU CYREG_PRT4_SLW

; MISO
MISO__0__MASK EQU 0x80
MISO__0__PC EQU CYREG_PRT4_PC7
MISO__0__PORT EQU 4
MISO__0__SHIFT EQU 7
MISO__AG EQU CYREG_PRT4_AG
MISO__AMUX EQU CYREG_PRT4_AMUX
MISO__BIE EQU CYREG_PRT4_BIE
MISO__BIT_MASK EQU CYREG_PRT4_BIT_MASK
MISO__BYP EQU CYREG_PRT4_BYP
MISO__CTL EQU CYREG_PRT4_CTL
MISO__DM0 EQU CYREG_PRT4_DM0
MISO__DM1 EQU CYREG_PRT4_DM1
MISO__DM2 EQU CYREG_PRT4_DM2
MISO__DR EQU CYREG_PRT4_DR
MISO__INP_DIS EQU CYREG_PRT4_INP_DIS
MISO__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
MISO__LCD_EN EQU CYREG_PRT4_LCD_EN
MISO__MASK EQU 0x80
MISO__PORT EQU 4
MISO__PRT EQU CYREG_PRT4_PRT
MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
MISO__PS EQU CYREG_PRT4_PS
MISO__SHIFT EQU 7
MISO__SLW EQU CYREG_PRT4_SLW

; MOSI
MOSI__0__MASK EQU 0x10
MOSI__0__PC EQU CYREG_PRT4_PC4
MOSI__0__PORT EQU 4
MOSI__0__SHIFT EQU 4
MOSI__AG EQU CYREG_PRT4_AG
MOSI__AMUX EQU CYREG_PRT4_AMUX
MOSI__BIE EQU CYREG_PRT4_BIE
MOSI__BIT_MASK EQU CYREG_PRT4_BIT_MASK
MOSI__BYP EQU CYREG_PRT4_BYP
MOSI__CTL EQU CYREG_PRT4_CTL
MOSI__DM0 EQU CYREG_PRT4_DM0
MOSI__DM1 EQU CYREG_PRT4_DM1
MOSI__DM2 EQU CYREG_PRT4_DM2
MOSI__DR EQU CYREG_PRT4_DR
MOSI__INP_DIS EQU CYREG_PRT4_INP_DIS
MOSI__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
MOSI__LCD_EN EQU CYREG_PRT4_LCD_EN
MOSI__MASK EQU 0x10
MOSI__PORT EQU 4
MOSI__PRT EQU CYREG_PRT4_PRT
MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
MOSI__PS EQU CYREG_PRT4_PS
MOSI__SHIFT EQU 4
MOSI__SLW EQU CYREG_PRT4_SLW

; SS
SS__0__MASK EQU 0x40
SS__0__PC EQU CYREG_PRT4_PC6
SS__0__PORT EQU 4
SS__0__SHIFT EQU 6
SS__AG EQU CYREG_PRT4_AG
SS__AMUX EQU CYREG_PRT4_AMUX
SS__BIE EQU CYREG_PRT4_BIE
SS__BIT_MASK EQU CYREG_PRT4_BIT_MASK
SS__BYP EQU CYREG_PRT4_BYP
SS__CTL EQU CYREG_PRT4_CTL
SS__DM0 EQU CYREG_PRT4_DM0
SS__DM1 EQU CYREG_PRT4_DM1
SS__DM2 EQU CYREG_PRT4_DM2
SS__DR EQU CYREG_PRT4_DR
SS__INP_DIS EQU CYREG_PRT4_INP_DIS
SS__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SS__LCD_EN EQU CYREG_PRT4_LCD_EN
SS__MASK EQU 0x40
SS__PORT EQU 4
SS__PRT EQU CYREG_PRT4_PRT
SS__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
SS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
SS__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
SS__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
SS__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
SS__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
SS__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
SS__PS EQU CYREG_PRT4_PS
SS__SHIFT EQU 6
SS__SLW EQU CYREG_PRT4_SLW

; Pin_5
Pin_5__0__MASK EQU 0x20
Pin_5__0__PC EQU CYREG_PRT15_PC5
Pin_5__0__PORT EQU 15
Pin_5__0__SHIFT EQU 5
Pin_5__AG EQU CYREG_PRT15_AG
Pin_5__AMUX EQU CYREG_PRT15_AMUX
Pin_5__BIE EQU CYREG_PRT15_BIE
Pin_5__BIT_MASK EQU CYREG_PRT15_BIT_MASK
Pin_5__BYP EQU CYREG_PRT15_BYP
Pin_5__CTL EQU CYREG_PRT15_CTL
Pin_5__DM0 EQU CYREG_PRT15_DM0
Pin_5__DM1 EQU CYREG_PRT15_DM1
Pin_5__DM2 EQU CYREG_PRT15_DM2
Pin_5__DR EQU CYREG_PRT15_DR
Pin_5__INP_DIS EQU CYREG_PRT15_INP_DIS
Pin_5__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
Pin_5__LCD_EN EQU CYREG_PRT15_LCD_EN
Pin_5__PORT EQU 15
Pin_5__PRT EQU CYREG_PRT15_PRT
Pin_5__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
Pin_5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
Pin_5__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
Pin_5__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
Pin_5__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
Pin_5__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
Pin_5__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
Pin_5__PS EQU CYREG_PRT15_PS
Pin_5__SLW EQU CYREG_PRT15_SLW

; Pin_6
Pin_6__0__MASK EQU 0x40
Pin_6__0__PC EQU CYREG_PRT6_PC6
Pin_6__0__PORT EQU 6
Pin_6__0__SHIFT EQU 6
Pin_6__AG EQU CYREG_PRT6_AG
Pin_6__AMUX EQU CYREG_PRT6_AMUX
Pin_6__BIE EQU CYREG_PRT6_BIE
Pin_6__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Pin_6__BYP EQU CYREG_PRT6_BYP
Pin_6__CTL EQU CYREG_PRT6_CTL
Pin_6__DM0 EQU CYREG_PRT6_DM0
Pin_6__DM1 EQU CYREG_PRT6_DM1
Pin_6__DM2 EQU CYREG_PRT6_DM2
Pin_6__DR EQU CYREG_PRT6_DR
Pin_6__INP_DIS EQU CYREG_PRT6_INP_DIS
Pin_6__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Pin_6__LCD_EN EQU CYREG_PRT6_LCD_EN
Pin_6__PORT EQU 6
Pin_6__PRT EQU CYREG_PRT6_PRT
Pin_6__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Pin_6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Pin_6__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Pin_6__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Pin_6__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Pin_6__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Pin_6__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Pin_6__PS EQU CYREG_PRT6_PS
Pin_6__SLW EQU CYREG_PRT6_SLW

; Pin_7
Pin_7__0__MASK EQU 0x10
Pin_7__0__PC EQU CYREG_PRT6_PC4
Pin_7__0__PORT EQU 6
Pin_7__0__SHIFT EQU 4
Pin_7__AG EQU CYREG_PRT6_AG
Pin_7__AMUX EQU CYREG_PRT6_AMUX
Pin_7__BIE EQU CYREG_PRT6_BIE
Pin_7__BIT_MASK EQU CYREG_PRT6_BIT_MASK
Pin_7__BYP EQU CYREG_PRT6_BYP
Pin_7__CTL EQU CYREG_PRT6_CTL
Pin_7__DM0 EQU CYREG_PRT6_DM0
Pin_7__DM1 EQU CYREG_PRT6_DM1
Pin_7__DM2 EQU CYREG_PRT6_DM2
Pin_7__DR EQU CYREG_PRT6_DR
Pin_7__INP_DIS EQU CYREG_PRT6_INP_DIS
Pin_7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
Pin_7__LCD_EN EQU CYREG_PRT6_LCD_EN
Pin_7__PORT EQU 6
Pin_7__PRT EQU CYREG_PRT6_PRT
Pin_7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
Pin_7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
Pin_7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
Pin_7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
Pin_7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
Pin_7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
Pin_7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
Pin_7__PS EQU CYREG_PRT6_PS
Pin_7__SLW EQU CYREG_PRT6_SLW

; Pin_8
Pin_8__0__MASK EQU 0x04
Pin_8__0__PC EQU CYREG_PRT2_PC2
Pin_8__0__PORT EQU 2
Pin_8__0__SHIFT EQU 2
Pin_8__AG EQU CYREG_PRT2_AG
Pin_8__AMUX EQU CYREG_PRT2_AMUX
Pin_8__BIE EQU CYREG_PRT2_BIE
Pin_8__BIT_MASK EQU CYREG_PRT2_BIT_MASK
Pin_8__BYP EQU CYREG_PRT2_BYP
Pin_8__CTL EQU CYREG_PRT2_CTL
Pin_8__DM0 EQU CYREG_PRT2_DM0
Pin_8__DM1 EQU CYREG_PRT2_DM1
Pin_8__DM2 EQU CYREG_PRT2_DM2
Pin_8__DR EQU CYREG_PRT2_DR
Pin_8__INP_DIS EQU CYREG_PRT2_INP_DIS
Pin_8__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
Pin_8__LCD_EN EQU CYREG_PRT2_LCD_EN
Pin_8__PORT EQU 2
Pin_8__PRT EQU CYREG_PRT2_PRT
Pin_8__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
Pin_8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
Pin_8__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
Pin_8__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
Pin_8__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
Pin_8__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
Pin_8__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
Pin_8__PS EQU CYREG_PRT2_PS
Pin_8__SLW EQU CYREG_PRT2_SLW

; Miscellaneous
; -- WARNING: define names containting LEOPARD or PANTHER are deprecated and will be removed in a future release
CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 0
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_MEMBER_5A EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_DIE_PANTHER EQU 2
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PANTHER
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
BCLK__BUS_CLK__HZ EQU 24000000
BCLK__BUS_CLK__KHZ EQU 24000
BCLK__BUS_CLK__MHZ EQU 24
CYDEV_APPLICATION_ID EQU 0x0000
CYDEV_APPLICATION_VERSION EQU 0x0000
CYDEV_BOOTLOADER_CHECKSUM EQU CYDEV_BOOTLOADER_CHECKSUM_BASIC
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
CYDEV_BOOTLOADER_FAST_VERIFY EQU 0
CYDEV_BOOTLOADER_VERSION EQU 0x0000
CYDEV_BOOTLOADER_WAIT_COMMAND EQU 1
CYDEV_BOOTLOADER_WAIT_TIME EQU 200
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x0E13C069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5A
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5A_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PANTHER_PRODUCTION
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CONFIGURATION_COMPRESSED EQU 0
CYDEV_CONFIGURATION_DMA EQU 1
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_DMA
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CUSTOM_ID EQU 0x00000000
CYDEV_DATA_CACHE_ENABLED EQU 0
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_REQXRES EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DEBUG_ENABLE_MASK EQU 0x01
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DBG_DBE
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x4000
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3 EQU 5
CYDEV_VIO3_MV EQU 5000
CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
